A Novel Hybrid Technique for Static Offset Voltage Calibration in Dynamic Comparators Leveraging Bulk Voltage and Shunt Current Trimming

Abstract

In this paper, a new hybrid digitally controlled circuit technique is proposed to calibrate the static offset voltage in the preamplifier stage for the Strong-Arm latch-based dynamic comparator with PMOS input transistors in 180nm CMOS technology. The fundamental idea for the proposed offset voltage calibration circuit technique is to balance the input drain currents in the preamplifier stage by adjusting the threshold voltage and connecting new shunt transistors. The hybrid circuit technique will combine two facts to calibrate the offset voltage. The first fact is that the voltage of the body terminal (VB) directly affects the threshold voltage (Vth). The second fact is related to the behavior of PMOS transistors. This integrated approach offers highly accurate and reliable offset voltage calibration. One of the advantages of the proposed technique is that it does not require any additional power supply or generate a voltage higher than the voltage source. It also eliminates the need for extra switches that could introduce a residual offset voltage. Moreover, this method supplies uninterrupted voltages to the bodies and gates, thereby enhancing the accuracy of the calibration procedure. The offset voltage calibration is performed in three phases, reducing from 3.9mV to 600µV with a power consumption of 56.8µW and a design area of 421µm2. This significant reduction enhances the precision of the calibration process, resulting in improved performance and accuracy for the comparator.